How to set the value of a macro using environment variable or command line in verilog?

I want to define a macro during runtime in Verilog using environment variable.

For example, I want to print some text to a file only when the DEBUG macro is set.

`define DEBUG 0
...
if(DEBUG) $fwrite(file,"Debug message");

How can I override the definition of DEBUG to 1 when ruing the simulation from command line or using environment variable?

Alteatively, I could keep the macro undefined and use ifdef

`ifdef(DEBUG) $fwrite(file,"Debug message");

In this case I would have to define the macro DEBUG when ruing the simulation. Is this possible?

I am using Modelsim. Thanks.