I have an example in Vivado 2014.2, consisting of a block ram with AXI lite through which I want to read and write, but it is not working. I have a simple testbench where I try this but I haven't managed to achieve this.
In particular the signals aw_ready, wready, rvalid and arready are never 1.
Could anyone point me to what the error is?
Here is the following code.
entity top is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
end top;
architecture Behavioral of top is
component memblock
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END component;
begin
memblock_instance : memblock
port map(
s_aclk => clk,
s_aresetn => rst,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
end Behavioral;
Here is the testbench code:
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
component top
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic;
signal s_axi_awaddr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal s_axi_awvalid : STD_LOGIC;
signal s_axi_awready : STD_LOGIC;
signal s_axi_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal s_axi_wstrb : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1111";
signal s_axi_wvalid : STD_LOGIC;
signal s_axi_wready : STD_LOGIC;
signal s_axi_bresp : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_bvalid : STD_LOGIC;
signal s_axi_bready : STD_LOGIC := '1';
signal s_axi_araddr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal s_axi_arvalid : STD_LOGIC;
signal s_axi_arready : STD_LOGIC;
signal s_axi_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal s_axi_rresp : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_rvalid : STD_LOGIC;
signal s_axi_rready : STD_LOGIC := '1';
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
top_inst : top port map(
clk => clk,
rst => rst,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
report "Start of simulation." severity note;
-- insert stimulus here
rst <= '0';
wait for 40 ns;
rst <= '1';
wait for 40 ns;
rst <= '0';
wait for 40 ns;
s_axi_awaddr <= (others=>'0');
s_axi_awvalid <= '1';
s_axi_wdata <= (others=>'0');
s_axi_arvalid <= '0';
wait for 20 ns;
s_axi_wvalid <= '0';
wait for 200 ns;
s_axi_awvalid <= '0';
wait for 200 ns;
--here starts Write operation
s_axi_awvalid <= '1';
s_axi_awaddr <= x"0000_0004";
wait for 20 ns;
s_axi_wdata <= x"0000_0001";
s_axi_wvalid <= '1';
wait for 40 ns;
s_axi_awvalid <= '0';
s_axi_wvalid <= '0';
wait for 100 ns;
s_axi_arvalid <= '1';
s_axi_araddr <= x"0000_0000";
wait for 10 ns;
s_axi_arvalid <= '0';
wait for 20 ns;
--here starts Read operation
s_axi_arvalid <= '1';
s_axi_araddr <= x"0000_0004";
wait for 20 ns;
s_axi_arvalid <= '0';
--End simulation
report "End of simulation.";
assert (false) severity failure; --This stops the simulation
end process;
END;
Also attached is an image of the waveform 
I really appreciate any help with this.