latch generation error in verilog 8bit processor code | بلاگ

latch generation error in verilog 8bit processor code

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I have encountered this error while synthesizing my 8 bit mips processor Verilog code in Xilinx

Xst:737 - Found 1-bit latch for signal <6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

what should I do to solve this? (as I'm new to Xilinx and making my first assignment on it ).

asked 41 secs ago
Marium H

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نویسنده : استخدام کار بازدید : 4 تاريخ : يکشنبه 24 تير 1397 ساعت: 16:29