I have encountered this error while synthesizing my 8 bit mips processor Verilog code in Xilinx
Xst:737 - Found 1-bit latch for signal <6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
what should I do to solve this? (as I'm new to Xilinx and making my first assignment on it ).